1. Field of the Invention
This invention relates to a semiconductor memory device, and more particularly to a NAND flash memory capable of storing multilevel data into a single memory cell using a plurality of bits.
2. Description of the Related Art
In a NAND flash memory, a plurality of cells arranged in the column direction are connected in series, thereby constituting a NAND cell. The drain side of the NAND cell is connected via a select gate to the corresponding bit line. Each bit line is connected to a write latch circuit and a read latch circuit. A read operation or a write operation is performed on all or half of the cells (e.g., 2 to 4 kB of cells) arranged in the row direction. The writing or reading unit is termed a page. In an erase operation, the threshold voltage of a memory cell is set to a negative voltage and electrons are injected into, for example, the floating gate of the memory cell by a write operation, thereby setting the threshold voltage to a positive voltage.
With the recent increase in the storage capacity, a multilevel memory which sets a plurality of threshold levels (threshold voltages) in a single cell and stores a plurality of bits of data has been developed (e.g., Jpn. Pat. Appln. KOKAI Publication No. 2004-192789). For example, when 4 threshold levels have been provided, 2 bits of data can be stored in one cell. When 8 threshold levels have been provided, 3 bits of data can be stored in one cell. When 16 threshold levels have been provided, 4 bits of data can be stored in one cell. When multilevel data is stored, a cell is composed of a plurality of pages. For example, when 4 threshold levels are provided in one cell, the cell is composed of 2 pages. When 8 threshold levels are provided in one cell, the cell is composed of 3 pages. When 16 threshold levels are provided in one cell, the cell is composed of 4 pages. Each page is specified by an address. The memory cell is written into, beginning with the first page.
When data is stored in a memory cell, the threshold level of a cell already written into might vary due to the influence of erroneous writing or the writing of data into an adjacent cell. As a result of a variation in the threshold level, the accuracy of the read-out data goes down. To improve the accuracy of the data, an Error-Correcting Code (ECC) is added to the data and a write operation or a read operation is carried out. Previously, when an ECC was stored, pages or sets of bits into which a page was divided were used as ECC processing units (hereinafter, referred to as ECC units).
The relationship between the threshold levels in a memory cell which stores 4-level, 8-level, and 16-level data and data written into the memory cell is as follows. For example, in a 4-level memory (4LC) which stores 2 bits in a cell, on the first page, if the threshold level is lower than read level (R Level) “2,” its data is “1” and, if the threshold level is higher than read level “2,” its data is “0.” However, on the second page, if the threshold level is lower than read level “1” or higher than read level “3,” its data is “1” and, if the threshold level is higher than read level “1” and lower than read level “3,” its data is “0.” Accordingly, the defect percentage of the second page is greater than that of the first page (second page>first page).
Furthermore, in an 8-level memory (8LC) which stores 3 bits in a cell, the defect percentage of the third page is greater than that of the second page and the defect percentage of the second page is greater than that of the first page (third page>second page>first page), meaning that the defect percentage of the third page is much greater than that of the first page. Moreover, in a 16-level memory (16LC) which stores 4 bits in a cell, the defect percentage of the fourth page is greater than that of the third page, the defect percentage of the third page is greater than that of the second page, and the defect percentage of the second page is greater than that of the first page (fourth page>third page>second page>first page), meaning that the defect percentage of the fourth page is much greater than that of the first page.
Accordingly, when a plurality of bits stored in a single cell are used as one ECC unit, this increases the ECC efficiency. However, the specifications of a conventional NAND flash memory are as follows: data is input to or read from cells page by page, starting with the beginning column address toward the end column address. Therefore, writing or reading data into or from the memory cells in ECC units has been desired.